Description:

This circuit allows you to transfer 8-bit words between two bus systems and may also function as a universal 8-bit shift register.

 

Functional Diagram and/or Package:

 

Pin Names:

  • Vdd - Positive Supply Voltage [3V to 15V]

  • Vss – Ground

  • AE - Tri-State Float

  • SD - Serial Data

  • A1 to A8 - Outputs for Buses

  • B1 to B8 - Dutputs for buses

  • CLK - Clock

  • A/S - Asynchronous or Synchronous (Mode Selection)

  • P/S - Parallel/Serial Moode Selection

  • A/B - Line Selection

 

Timing Diagram:

 

 

Operation Mode:

  • A “'1” applied to the input allows data transfer into the register via the parallel data lines.

  • The signals are transferredwith the positive transition of the clok Signal.

The control lines determine what the device is going to do:
  • If A/B line selection is “'1” then the eight A-bus lines operate a inputs and the eight B-bus lines act as outputs.

  • If A/B line selection is “0” then the eight B-lines are now inputs and the eight A-bus lines act as outputs.

  • The AE inputs are a feature that allows many registers to feed data to a common bus. The A date lines are enabled only when this input is “1”

  • Data storage through recirculation of data in each register is accomplished by making the A/B input “'1 ” and AE “0””.

  • When the Asynchronous/Synchronous [A/S] line is “1” transfer occurs immediately. If “0” the transfer occurs with the positive transition of the clock input.

  • If the P/S line is “1” the circuit is in the parallel data load mode. If in the “0” logic level, data is serially loaded. When serially loaded, data is transferred from stage to stage With the positive transition of the clock signal.

  • P/S line must be “0” When P/S is “1” because asynchronous serial operation is not possible With this device.

 

Electrical Characteristics:

 

 

Applications:

  • General Purpose Register [PIPO SIPO, SlSO]

  • Phase and Frequency Comparators

  • Double Bus Register Systems

  • Address and Buffer Registers

  • Shift Right/Shift Left Registers (With parallel loading]

  • Johnson Ring Counters

  • Pseudo-Random Code Generators

  • Sample and Hold Registers

 

Observations:

Register expansion can be accomplished by simply cascading devices.

 

Datasheets


N° of component