Written by: Newton C. Braga

The input frequency of a signal applied to this circuit will be divided by one to 9999 in this CMOS circuit. The maximum input frequency is 6 MHz and the circuit can be powered from 6 to 15 V supplies. Current drain is very low. More stages can be added for divisions above 9999.

 

Programmable Frequency Divider 1 to 9999
Programmable Frequency Divider 1 to 9999