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Description: This device is formed by four D-type latches with level-controlled storage command pins.
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Functional Diagram and/or Package:
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Pin Names:
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Vdd - Positive Supply Voltage [BV to 15V]
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Vss - Ground
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D1, D2, D3, D4 - D Inputs
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Q1, Q2, Q3, Q4 - Outputs
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Q1/, Q2/, Q3/, Q4/ - Complementary Outputs
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CLK - Clock
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PL – Polarity
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Truth Table:
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Operation Mode:
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With PL=0 and ST=0, data applied to D appears in the outputs [Q and (Q/).
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Passing PL to “1' data in the input is stored at the negative transition of the clock pulse.
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The output follows one state of the Store Control.
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Electrical Characteristics:
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Applications:
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Buffer Storage ' Digital Logic ' Holding Registers
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Observations:
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Stages using this device may not be cascaded.
