The buffered phase shift oscillator circuit shown in the figure oscillates at a frequency of 2.9 kHz, which is closer to the calculated ideal frequency of 2.76 kHz and it manages to oscillate with a gain of 8.33 which is also fine close to the calculated value 8. The amplifier / isolator buffers or stages prevent the RC sections from loading each other and with that the oscillator can work much closer to the calculated gain and frequency values. The gain, fixed by the resistor Rc, loads the third RC section and if a fourth operational amplifier, in a configuration with 4 of them, buffer this section, the performance becomes ideal. Sinusoidal signals with low distortion can be obtained from the output of each amplifier, but the best signal will be in the last RC section. This is a high impedance node, which means that the excited circuit must have a high impedance to avoid a load and a frequency shift caused by possible variations in that load.
